1. Field of the Invention
The present invention relates to semiconductor processing and, in particular, to the fabrication of integrated circuits using selective etching of single-crystal semiconductor relative to polycrystalline or amorphous semiconductor to manufacture vertical dynamic random access memory (DRAM) and other devices.
2. Description of Related Art
Vertical dynamic random access memory (DRAM) circuits and devices have been employed to reduce effective cell size and increase memory density. Typically a vertical DRAM memory cell comprises a capacitor in the lower portion of the trench, with the vertical metal oxide semiconductor field effect transistor (MOSFET) in the upper portion of the trench. The top portion of the trench has an octagonal shape after deep trench etch. It is usually desired to transform the shape of the upper trench portion to a rectangular shape to improve process margin and device performance.
A prior art method for trench shaping the MOSFET is shown in FIGS. 1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b and 5. FIGS. 1a and 1b show an intermediate structure in which a trench has been etched in a single crystal semiconductor substrate 20 through an upper pad nitride layer 32 and a lower pad oxide layer 30. A capacitor is formed having node dielectric 24 along the sidewall of the lower trench of substrate 20 and an oxide collar 26 disposed along the sidewall above the trench capacitor. The lower trench is filled with amorphous or polycrystalline semiconductor (polysilicon) 22 and the polysilicon 22 is recessed above the collar 26 to later form adjacent buried strap diffusion regions 46 in FIG. 5. The buried strap regions 46 form an electrical bridge from the capacitor to the upper MOSFET region to be formed in the upper trench portion. The upper trench has an octagonal shape in plan view, as shown in FIG. 1b. 
Since the upper trench sidewall 28 is exposed, a crystallographic orientation dependent silicon etch can be performed to change the shape to a rectangle. However, before shaping the upper trench, as shown in FIGS. 2a and 2b a trench top oxide (TTO) 34 is deposited atop the polysilicon 22 to prevent the polysilicon 22 from being etched. As shown in FIGS. 3a and 3b, the exposed trench sidewall 28 is then etched to form new sidewalls 28′ in the upper trench having a rectangular shape in plan view (FIG. 3b). Optionally, the exposed edge portions of pad oxide 30 and pad nitride 32 are also etched to have their edges aligned with the new sidewalls 28′. As a result of such prior art trench shaping, sharp corners 36 are formed in the substrate walls between the vertical sidewall 28′ of substrate 20 and horizontal wall portion 28′a of substrate 20 adjacent to and outside the top surface of TTO 34. When the gate oxide is grown in the trench, as shown in FIGS. 4a and 4b, it is formed as oxide layer 38 on the vertical sidewalls and oxide layer 38a on the horizontal wall. The oxide layer is thinner at sharp corners 36′, as shown in the enlarged portion of FIG. 4a. Even if a uniform oxide 38 can be grown, a high electrical field can be produced at these corners 36′ due to the geometric effect. FIG. 5 shows a complete DRAM cell with a vertical MOSFET formed in the shaped upper trench comprising filled gate conductor 40 such as polysilicon, a first n+ doped source/drain terminal 44, and a second n+ source/drain terminal—the buried strap diffusion region 46. An oxide layer 42 may be formed to cover the n+ doped layer 44. The combination of thinner gate oxide and the higher electric field in this prior art DRAM construction at corners 36′ shown in FIG. 4a degrades device performance and causes severe reliability problems. Furthermore, the isolation between gate poly 40 above TTO 34 and the polysilicon 22 below the TTO relies on both the TTO and gate oxide layer 38. Since the thickness of the TTO at typically about 30 nm is usually much greater than the thickness of the gate oxide at typically about 6 nm, the thin gate oxide results in poor isolation of the vertical MOSFET.
Selective etch is very important in semiconductor manufacturing. It is well known that hydroxide, including ammonium hydroxide (NH4OH) solution and alkaline solutions such as KOH, etches silicon. Organic solutions such as tetramethylammonium hydroxide (TMAH), hydrazine, and ethylene diamine pyrocatechol (EDP) can also be used to etch silicon. Alkaline solutions have the drawback of metal contamination (e.g., KOH will plate out potassium ions), and organic solutions are usually toxic, unstable, and difficult to handle. In contrast, NH4OH does not contain any metal ions and thus is compatible with semiconductor processing. It is much less toxic compared with organic solutions. Due to these distinct advantages, NH4OH has been widely adopted in semiconductor manufacturing to etch silicon. Use of NH4OH is described in U.S. Pat. Nos. 4,681,657, 5,030,590 and 5,976,767. It has also been previously known in the art that the process is electrochemical, that doping of silicon will affect etch rate and selectivity can be gained this way. Further, it has been known that NH4OH etches amorphous or polycrystalline semiconductor at a much faster rate than single-crystal semiconductor, to permit amorphous or polycrystalline semiconductor to be etched selectively to single-crystal semiconductor. For example, such a selective etch process has been used to form a buried strap in a vertical transistor DRAM of the type described above. While in many other applications there is a need to etch single-crystal semiconductor selective to amorphous or polycrystalline semiconductor, no prior art method has been able to achieve this purpose.